Programmable logic devices (PLDs) are a well-known type of programmable integrated circuit (IC) that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
The configuration data for programming an FPGA is generated by using design tools to prepare and compile a high-level circuit design. The tools generally synthesize the high-level design into a netlist, map elements of the netlist to resources of the target device, and place and route the mapped resources on particular resources of the target device. For devices such as FPGAs, synthesis tools may be programmed with hardcoded patterns for finding structures such as digital signal processors (DSPs), multiplexers, adders, or combinations of objects in the design, and mapping those structures to particular device resources. The particular mappings of structures to resources may be optimized for speed, area, or power consumption, for example.